From acba73aefcbd7dacb547b61570a1836b745be2e5 Mon Sep 17 00:00:00 2001 From: "Jonathan A. Kollasch" Date: Mon, 20 Jul 2015 09:51:34 -0500 Subject: nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h Based on the observations that AMD Fam10h with both Nvidia CK804 (Asus KFSN4-DRE) and MCP55 (Sun Ultra 40 M2) need to avoid adjusting the LPC bridge register 0x78 (particularly the 0x7b byte) to get to ramstage: Assume that there's something about this register that adjusting it the way we do for K8 is something that can/should be universally avoided on all Fam10h systems with these chipsets. Change-Id: I1eceeb20ecaefef4c61c11e19d1f5a59f91a0a2f Signed-off-by: Jonathan A. Kollasch Reviewed-on: http://review.coreboot.org/10984 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson --- src/southbridge/nvidia/mcp55/early_setup_car.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/southbridge/nvidia/mcp55') diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 4970a4cf9a..d919610900 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -242,7 +242,17 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + /* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in mcp55_early_setup_x() on Fam10h systems by not touching 0x78. + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#else RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, +#endif #if CONFIG_MCP55_USE_AZA RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, -- cgit v1.2.3