From a144e4d6fa93b9ba129b3aa8991cc5fb2ec3c8a6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 23 May 2018 20:00:16 +0300 Subject: device: Use pcidev_path_behind() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iac16f9412d0e6aac908d873c61a4de3935e5318a Signed-off-by: Kyösti Mälkki Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/26518 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/southbridge/nvidia/mcp55/mcp55.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/southbridge/nvidia/mcp55') diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index 551da8937c..8f0ec8fe77 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -30,7 +30,7 @@ static struct device *find_lpc_dev(struct device *dev, unsigned devfn) { struct device *lpc_dev; - lpc_dev = dev_find_slot(dev->bus->secondary, devfn); + lpc_dev = pcidev_path_behind(dev->bus, devfn); if (!lpc_dev) return lpc_dev; @@ -158,7 +158,7 @@ void mcp55_enable(struct device *dev) return; if (index2 != 0) { - sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); + sm_dev = pcidev_path_behind(dev->bus, devfn + 1); if (!sm_dev) return; if (sm_dev) { @@ -187,7 +187,7 @@ void mcp55_enable(struct device *dev) } if (index == 16) { - sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); + sm_dev = pcidev_path_behind(dev->bus, devfn + 1); if (!sm_dev) return; @@ -211,7 +211,7 @@ void mcp55_enable(struct device *dev) /* NIC1 is the final, we need update final reg to 0xe8. */ if (index == 9) { - sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); + sm_dev = pcidev_path_behind(dev->bus, devfn + 1); if (!sm_dev) return; reg_old = pci_read_config32(sm_dev, 0xe8); -- cgit v1.2.3