From 1ca978ee6529251ed80b47da679be7adc75fa46a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:28:43 +0100 Subject: sb/nvidia/mcp55: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I7cd33316140f2cdc83949aa5db7e6f1565982543 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36973 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/nvidia/mcp55/ide.c | 78 -------------------------------------- 1 file changed, 78 deletions(-) delete mode 100644 src/southbridge/nvidia/mcp55/ide.c (limited to 'src/southbridge/nvidia/mcp55/ide.c') diff --git a/src/southbridge/nvidia/mcp55/ide.c b/src/southbridge/nvidia/mcp55/ide.c deleted file mode 100644 index 36e20b4aa0..0000000000 --- a/src/southbridge/nvidia/mcp55/ide.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include "chip.h" -#include "mcp55.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_nvidia_mcp55_config *conf; - u32 dword; - u16 word; - u8 byte; - conf = dev->chip_info; - - word = pci_read_config16(dev, 0x50); - /* Ensure prefetch is disabled. */ - word &= ~((1 << 15) | (1 << 13)); - if (conf->ide1_enable) { - /* Enable secondary IDE interface. */ - word |= (1 << 0); - printk(BIOS_DEBUG, "IDE1\t"); - } - if (conf->ide0_enable) { - /* Enable primary IDE interface. */ - word |= (1 << 1); - printk(BIOS_DEBUG, "IDE0\n"); - } - - word |= (1 << 12); - word |= (1 << 14); - - pci_write_config16(dev, 0x50, word); - - byte = 0x20; /* Latency: 64-->32 */ - pci_write_config8(dev, 0xd, byte); - - dword = pci_read_config32(dev, 0xf8); - dword |= 12; - pci_write_config32(dev, 0xf8, dword); -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, -// .enable = mcp55_enable, - .ops_pci = &mcp55_pci_ops, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_IDE, -}; -- cgit v1.2.3