From fc7bc54e34d496a9fe2d0047eddeb9d1f48de417 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 21 Jun 2020 17:42:52 +0200 Subject: sb/intel/common: Add early SPI code All Intel southbridges with SPI perform this write. Put it inside a function in common code. Use a different name to avoid a name clash. As it is only one statement, make it inline so that it can be defined on the header itself. It is only called once per southbridge anyway. Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42660 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/common/early_spi.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 src/southbridge/intel/common/early_spi.h (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/common/early_spi.h b/src/southbridge/intel/common/early_spi.h new file mode 100644 index 0000000000..ae84f74e83 --- /dev/null +++ b/src/southbridge/intel/common/early_spi.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H +#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H + +#include + +static inline void enable_spi_prefetching_and_caching(void) +{ + pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xdc, ~(3 << 2), 2 << 2); +} + +#endif -- cgit v1.2.3