From f0ed846cfce843965f191e56ba01b35d8c9195b0 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 2 May 2022 16:52:57 +0200
Subject: arch/x86/acpi: Consolidate POST code handling

Move ASL POST code declarations into a common file to avoid redundancy.
Also, provide a dummy implementation when `POST_IO` is not enabled, as
the value of `CONFIG_POST_IO_PORT` can't be used.

Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
---
 src/southbridge/intel/common/acpi/platform.asl | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

(limited to 'src/southbridge/intel')

diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl
index ec7d680ded..e044f04822 100644
--- a/src/southbridge/intel/common/acpi/platform.asl
+++ b/src/southbridge/intel/common/acpi/platform.asl
@@ -9,13 +9,7 @@ Field (APMP, ByteAcc, NoLock, Preserve)
 	APMS, 8		// APM status
 }
 
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
-	DBG0, 8
-}
+#include <arch/x86/acpi/post.asl>
 
 #if CONFIG(ACPI_SOC_NVS)
 /* SMI I/O Trap */
-- 
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