From d6ccbb9d48f97dd3bbd4b947fe3bc4857216a363 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 15 Jan 2021 13:46:11 +0200 Subject: mainboards: Drop PWRS from GNVS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352 Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 2 +- src/southbridge/intel/bd82x6x/include/soc/nvs.h | 2 +- src/southbridge/intel/i82801gx/acpi/globalnvs.asl | 2 +- src/southbridge/intel/i82801gx/include/soc/nvs.h | 2 +- src/southbridge/intel/i82801ix/acpi/globalnvs.asl | 2 +- src/southbridge/intel/i82801ix/include/soc/nvs.h | 2 +- src/southbridge/intel/i82801jx/acpi/globalnvs.asl | 2 +- src/southbridge/intel/i82801jx/include/soc/nvs.h | 2 +- src/southbridge/intel/ibexpeak/acpi/globalnvs.asl | 2 +- src/southbridge/intel/ibexpeak/include/soc/nvs.h | 2 +- src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 2 +- src/southbridge/intel/lynxpoint/include/soc/nvs.h | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 20e32efa6f..0d798b8ca2 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PRM5, 8, // 0x0a - Lock function parameter P80D, 32, // 0x0b - Debug port (IO 0x80) value LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) + , 8, // 0x10 - Power State (AC = 1) /* Thermal policy */ Offset (0x11), TLVL, 8, // 0x11 - Throttle Level Limit diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h index 1c33b0cd73..95bf91bcb6 100644 --- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h +++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h @@ -19,7 +19,7 @@ struct __packed global_nvs { u8 prm5; /* 0x0a - Lock function parameter */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ + u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */ /* Thermal policy */ u8 tlvl; /* 0x11 - Throttle Level Limit */ u8 flvl; /* 0x12 - Current FAN Level */ diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index a3b15b68d7..a1706a725f 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PRM5, 8, // 0x0a - Lock function parameter P80D, 32, // 0x0b - Debug port (IO 0x80) value LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) + , 8, // 0x10 - Power State (AC = 1) DBGS, 8, // 0x11 - Debug State LINX, 8, // 0x12 - Linux OS DCKN, 8, // 0x13 - PCIe docking state diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h index 933921c3f4..93272dc018 100644 --- a/src/southbridge/intel/i82801gx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h @@ -19,7 +19,7 @@ struct __packed global_nvs { u8 prm5; /* 0x0a - Lock function parameter */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ + u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */ u8 dbgs; /* 0x11 - Debug state */ u8 linx; /* 0x12 - Linux OS */ u8 dckn; /* 0x13 - PCIe docking state */ diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index f408a8c53a..55a368eecc 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PRM5, 8, // 0x0a - Lock function parameter P80D, 32, // 0x0b - Debug port (IO 0x80) value LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) + , 8, // 0x10 - Power State (AC = 1) DBGS, 8, // 0x11 - Debug State LINX, 8, // 0x12 - Linux OS DCKN, 8, // 0x13 - PCIe docking state diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h index 3c9aac90a2..5ae7f25772 100644 --- a/src/southbridge/intel/i82801ix/include/soc/nvs.h +++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h @@ -19,7 +19,7 @@ struct __packed global_nvs { u8 prm5; /* 0x0a - Lock function parameter */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ + u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */ u8 dbgs; /* 0x11 - Debug state */ u8 linx; /* 0x12 - Linux OS */ u8 dckn; /* 0x13 - PCIe docking state */ diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 264b52a3b0..2b3e21b188 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PRM5, 8, // 0x0a - Lock function parameter P80D, 32, // 0x0b - Debug port (IO 0x80) value LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) + , 8, // 0x10 - Power State (AC = 1) DBGS, 8, // 0x11 - Debug State LINX, 8, // 0x12 - Linux OS DCKN, 8, // 0x13 - PCIe docking state diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h index 54c4a2c7c4..96c55882e8 100644 --- a/src/southbridge/intel/i82801jx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h @@ -18,7 +18,7 @@ struct __packed global_nvs { u8 prm5; /* 0x0a - Lock function parameter */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ + u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */ u8 dbgs; /* 0x11 - Debug state */ u8 linx; /* 0x12 - Linux OS */ u8 dckn; /* 0x13 - PCIe docking state */ diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl index 46c6f4f958..8525633e60 100644 --- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl +++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl @@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PRM5, 8, // 0x0a - Lock function parameter P80D, 32, // 0x0b - Debug port (IO 0x80) value LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) + , 8, // 0x10 - Power State (AC = 1) /* Thermal policy */ Offset (0x11), TLVL, 8, // 0x11 - Throttle Level Limit diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h index 03897cd4b7..f552a02b09 100644 --- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h +++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h @@ -20,7 +20,7 @@ struct __packed global_nvs { u8 prm5; /* 0x0a - Lock function parameter */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ + u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */ /* Thermal policy */ u8 tlvl; /* 0x11 - Throttle Level Limit */ u8 flvl; /* 0x12 - Current FAN Level */ diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 1b06beb7b6..d0c08a14be 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PRM5, 8, // 0x0a - Lock function parameter P80D, 32, // 0x0b - Debug port (IO 0x80) value LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) + , 8, // 0x10 - Power State (AC = 1) /* Thermal policy */ Offset (0x11), TLVL, 8, // 0x11 - Throttle Level Limit diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h index 7db206e6e9..5bda60d95a 100644 --- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h +++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h @@ -19,7 +19,7 @@ struct __packed global_nvs { u8 prm5; /* 0x0a - Lock function parameter */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ + u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */ /* Thermal policy */ u8 tlvl; /* 0x11 - Throttle Level Limit */ u8 flvl; /* 0x12 - Current FAN Level */ -- cgit v1.2.3