From d303311ce20c18ce8d7ebb68f937346a099d097a Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 13 Jul 2017 10:27:45 -0700 Subject: sb/intel/fspi89xx: Fix timestamp code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The save_timestamp_to_cmos code was used at Sage before the early cbmem was available. Update it to use the standard timestamp calls, based on the rangeley implementation. Change-Id: I9a3a6609bdc8d03c4b86951daa1cafddd9c1332e Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20564 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/fsp_i89xx/romstage.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index 385e4d6ba3..a08972024f 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -99,9 +99,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x40); -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - save_timestamp_to_cmos(CMOS_MAIN_START_ADDR, rdtsc()); -#endif + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + pch_enable_lpc(); /* Enable GPIOs */ @@ -151,9 +151,7 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x48); -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - save_timestamp_to_cmos(CMOS_PRE_INITRAM_ADDR, rdtsc()); -#endif + timestamp_add_now(TS_BEFORE_INITRAM); /* * Call early init to initialize memory and chipset. This function returns -- cgit v1.2.3