From cf39f89fd9bc1177670da55a1432ce0631549f1f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 21 Jun 2020 18:00:43 +0200 Subject: sb/intel/i82801gx: Use common early SPI code Change-Id: I44de4698d062508dd24f37b37014e09d95726c71 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/i82801gx/bootblock.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index b0f73e84fc..51fb24f6fa 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -2,22 +2,12 @@ #include #include +#include #include "i82801gx.h" -static void enable_spi_prefetch(void) -{ - u8 reg8; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, BIOS_CNTL, reg8); -} - void bootblock_early_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetching_and_caching(); i82801gx_setup_bars(); -- cgit v1.2.3