From c9ee2c0323e0e9fb2094651eac383898057cc2ab Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 21 Jun 2020 17:58:59 +0200 Subject: sb/intel/bd82x6x: Use common early SPI code Change-Id: If4843e93c993ed2de60b2b6064c2c9e98637ce9a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42661 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/southbridge/intel/bd82x6x/bootblock.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 3a99f512c6..a3228e7e52 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -2,16 +2,9 @@ #include #include +#include #include "pch.h" -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - pci_update_config8(PCH_LPC_DEV, BIOS_CNTL, ~(3 << 2), 2 << 2); -} - static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC */ @@ -40,7 +33,7 @@ static void set_spi_speed(void) void bootblock_early_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetching_and_caching(); early_pch_init(); -- cgit v1.2.3