From c9b13594eb8d425e54a126b5c10e3f6fbc41528b Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 29 Nov 2019 11:47:47 +0100 Subject: src/: Remove g_ prefixes and _g suffixes from variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These were often used to distinguish CAR_GLOBAL variables that weren't directly usable. Since we're getting rid of this special case, also get rid of the marker. This change was created using coccinelle and the following script: @match@ type T; identifier old =~ "^(g_.*|.*_g)$"; @@ old @script:python global_marker@ old << match.old; new; @@ new = old if old[0:2] == "g_": new = new[2:] if new[-2:] == "_g": new = new[:-2] coccinelle.new = new @@ identifier match.old, global_marker.new; @@ - old + new @@ type T; identifier match.old, global_marker.new; @@ - T old; + T new; @@ type T; identifier match.old, global_marker.new; @@ - T old + T new = ...; There were some manual fixups: Some code still uses the global/local variable naming scheme, so keep g_* there, and some variable names weren't completely rewritten. Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: HAOUAS Elyes --- src/southbridge/intel/common/spi.c | 182 ++++++++++++++++++------------------- 1 file changed, 91 insertions(+), 91 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 4974e08c65..cf678176ab 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -111,7 +111,7 @@ struct ich_spi_controller { uint8_t fpr_max; }; -static struct ich_spi_controller g_cntlr; +static struct ich_spi_controller cntlr; enum { SPIS_SCIP = 0x0001, @@ -260,9 +260,9 @@ static void ich_set_bbar(uint32_t minaddr) uint32_t ichspi_bbar; minaddr &= bbar_mask; - ichspi_bbar = readl_(g_cntlr.bbar) & ~bbar_mask; + ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; ichspi_bbar |= minaddr; - writel_(ichspi_bbar, g_cntlr.bbar); + writel_(ichspi_bbar, cntlr.bbar); } #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) @@ -305,42 +305,42 @@ void spi_init(void) if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { ich7_spi = get_spi_bar(dev); - g_cntlr.ich7_spi = ich7_spi; - g_cntlr.opmenu = ich7_spi->opmenu; - g_cntlr.menubytes = sizeof(ich7_spi->opmenu); - g_cntlr.optype = &ich7_spi->optype; - g_cntlr.addr = &ich7_spi->spia; - g_cntlr.data = (uint8_t *)ich7_spi->spid; - g_cntlr.databytes = sizeof(ich7_spi->spid); - g_cntlr.status = (uint8_t *)&ich7_spi->spis; - g_cntlr.control = &ich7_spi->spic; - g_cntlr.bbar = &ich7_spi->bbar; - g_cntlr.preop = &ich7_spi->preop; - g_cntlr.fpr = &ich7_spi->pbr[0]; - g_cntlr.fpr_max = 3; + cntlr.ich7_spi = ich7_spi; + cntlr.opmenu = ich7_spi->opmenu; + cntlr.menubytes = sizeof(ich7_spi->opmenu); + cntlr.optype = &ich7_spi->optype; + cntlr.addr = &ich7_spi->spia; + cntlr.data = (uint8_t *)ich7_spi->spid; + cntlr.databytes = sizeof(ich7_spi->spid); + cntlr.status = (uint8_t *)&ich7_spi->spis; + cntlr.control = &ich7_spi->spic; + cntlr.bbar = &ich7_spi->bbar; + cntlr.preop = &ich7_spi->preop; + cntlr.fpr = &ich7_spi->pbr[0]; + cntlr.fpr_max = 3; } else { ich9_spi = get_spi_bar(dev); - g_cntlr.ich9_spi = ich9_spi; + cntlr.ich9_spi = ich9_spi; hsfs = readw_(&ich9_spi->hsfs); - g_cntlr.hsfs = hsfs; - g_cntlr.opmenu = ich9_spi->opmenu; - g_cntlr.menubytes = sizeof(ich9_spi->opmenu); - g_cntlr.optype = &ich9_spi->optype; - g_cntlr.addr = &ich9_spi->faddr; - g_cntlr.data = (uint8_t *)ich9_spi->fdata; - g_cntlr.databytes = sizeof(ich9_spi->fdata); - g_cntlr.status = &ich9_spi->ssfs; - g_cntlr.control = (uint16_t *)ich9_spi->ssfc; - g_cntlr.bbar = &ich9_spi->bbar; - g_cntlr.preop = &ich9_spi->preop; - g_cntlr.fpr = &ich9_spi->pr[0]; - g_cntlr.fpr_max = 5; - - if (g_cntlr.hsfs & HSFS_FDV) { + cntlr.hsfs = hsfs; + cntlr.opmenu = ich9_spi->opmenu; + cntlr.menubytes = sizeof(ich9_spi->opmenu); + cntlr.optype = &ich9_spi->optype; + cntlr.addr = &ich9_spi->faddr; + cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.databytes = sizeof(ich9_spi->fdata); + cntlr.status = &ich9_spi->ssfs; + cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.bbar = &ich9_spi->bbar; + cntlr.preop = &ich9_spi->preop; + cntlr.fpr = &ich9_spi->pr[0]; + cntlr.fpr_max = 5; + + if (cntlr.hsfs & HSFS_FDV) { writel_(4, &ich9_spi->fdoc); - g_cntlr.flmap0 = readl_(&ich9_spi->fdod); + cntlr.flmap0 = readl_(&ich9_spi->fdod); writel_(0x1000, &ich9_spi->fdoc); - g_cntlr.flcomp = readl_(&ich9_spi->fdod); + cntlr.flcomp = readl_(&ich9_spi->fdod); } } @@ -358,9 +358,9 @@ void spi_init(void) static int spi_locked(void) { if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { - return !!(readw_(&g_cntlr.ich7_spi->spis) & HSFS_FLOCKDN); + return !!(readw_(&cntlr.ich7_spi->spis) & HSFS_FLOCKDN); } else { - return !!(readw_(&g_cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN); + return !!(readw_(&cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN); } } @@ -436,10 +436,10 @@ static int spi_setup_opcode(spi_transaction *trans) spi_use_out(trans, 1); if (!spi_locked()) { /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, g_cntlr.opmenu); - optypes = readw_(g_cntlr.optype); + writeb_(trans->opcode, cntlr.opmenu); + optypes = readw_(cntlr.optype); optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, g_cntlr.optype); + writew_(optypes, cntlr.optype); return 0; } @@ -451,7 +451,7 @@ static int spi_setup_opcode(spi_transaction *trans) if (trans->opcode == SPI_OPCODE_WREN) return 0; - read_reg(g_cntlr.opmenu, opmenu, sizeof(opmenu)); + read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; @@ -463,7 +463,7 @@ static int spi_setup_opcode(spi_transaction *trans) return -1; } - optypes = readw_(g_cntlr.optype); + optypes = readw_(cntlr.optype); optype = (optypes >> (opcode_index * 2)) & 0x3; if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && @@ -512,10 +512,10 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) u16 status = 0; while (timeout--) { - status = readw_(g_cntlr.status); + status = readw_(cntlr.status); if (wait_til_set ^ ((status & bitmask) == 0)) { if (wait_til_set) - writew_((status & bitmask), g_cntlr.status); + writew_((status & bitmask), cntlr.status); return status; } udelay(10); @@ -528,9 +528,9 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) static int spi_is_multichip(void) { - if (!(g_cntlr.hsfs & HSFS_FDV)) + if (!(cntlr.hsfs & HSFS_FDV)) return 0; - return !!((g_cntlr.flmap0 >> 8) & 3); + return !!((cntlr.flmap0 >> 8) & 3); } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, @@ -561,7 +561,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1; - writew_(SPIS_CDS | SPIS_FCERR, g_cntlr.status); + writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); spi_setup_type(&trans); if ((opcode_index = spi_setup_opcode(&trans)) < 0) @@ -576,7 +576,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * issuing a transaction between WREN and DATA. */ if (!spi_locked()) - writew_(trans.opcode, g_cntlr.preop); + writew_(trans.opcode, cntlr.preop); return 0; } @@ -584,13 +584,13 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, control = SPIC_SCGO | ((opcode_index & 0x07) << 4); /* Issue atomic preop cycle if needed */ - if (readw_(g_cntlr.preop)) + if (readw_(cntlr.preop)) control |= SPIC_ACS; if (!trans.bytesout && !trans.bytesin) { /* SPI addresses are 24 bit only */ if (with_address) - writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); /* * This is a 'no data' command (like Write Enable), its @@ -598,7 +598,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * spi_setup_opcode() above. Tell the chip to send the * command. */ - writew_(control, g_cntlr.control); + writew_(control, cntlr.control); /* wait for the result */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -620,7 +620,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * and followed by other SPI commands, and this sequence is controlled * by the SPI chip driver. */ - if (trans.bytesout > g_cntlr.databytes) { + if (trans.bytesout > cntlr.databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" " spi_crop_chunk()?\n"); return -1; @@ -634,28 +634,28 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, uint32_t data_length; /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); if (trans.bytesout) - data_length = min(trans.bytesout, g_cntlr.databytes); + data_length = min(trans.bytesout, cntlr.databytes); else - data_length = min(trans.bytesin, g_cntlr.databytes); + data_length = min(trans.bytesin, cntlr.databytes); /* Program data into FDATA0 to N */ if (trans.bytesout) { - write_reg(trans.out, g_cntlr.data, data_length); + write_reg(trans.out, cntlr.data, data_length); spi_use_out(&trans, data_length); if (with_address) trans.offset += data_length; } /* Add proper control fields' values */ - control &= ~((g_cntlr.databytes - 1) << 8); + control &= ~((cntlr.databytes - 1) << 8); control |= SPIC_DS; control |= (data_length - 1) << 8; /* write it */ - writew_(control, g_cntlr.control); + writew_(control, cntlr.control); /* Wait for Cycle Done Status or Flash Cycle Error. */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -668,7 +668,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, } if (trans.bytesin) { - read_reg(g_cntlr.data, trans.in, data_length); + read_reg(cntlr.data, trans.in, data_length); spi_use_in(&trans, data_length); if (with_address) trans.offset += data_length; @@ -677,7 +677,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, spi_xfer_exit: /* Clear atomic preop now that xfer is done */ - writew_(0, g_cntlr.preop); + writew_(0, cntlr.preop); return 0; } @@ -685,9 +685,9 @@ spi_xfer_exit: /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { - uint32_t addr_old = readl_(&g_cntlr.ich9_spi->faddr) & ~0x01FFFFFF; + uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; - writel_((addr & 0x01FFFFFF) | addr_old, &g_cntlr.ich9_spi->faddr); + writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr); } /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. @@ -701,17 +701,17 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, uint32_t addr; timeout /= 8; /* scale timeout duration to counter */ - while ((((hsfs = readw_(&g_cntlr.ich9_spi->hsfs)) & + while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) & (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout) { udelay(8); } - writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); if (!timeout) { uint16_t hsfc; - addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&g_cntlr.ich9_spi->hsfc); + addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&cntlr.ich9_spi->hsfc); printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -721,8 +721,8 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, if (hsfs & HSFS_FCERR) { uint16_t hsfc; - addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&g_cntlr.ich9_spi->hsfc); + addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&cntlr.ich9_spi->hsfc); printk(BIOS_ERR, "Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -758,17 +758,17 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, while (offset < end) { /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ - writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); ich_hwseq_set_addr(offset); offset += erase_size; - hsfc = readw_(&g_cntlr.ich9_spi->hsfc); + hsfc = readw_(&cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &g_cntlr.ich9_spi->hsfc); + writew_(hsfc, &cntlr.ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, len)) { printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); ret = -1; @@ -790,7 +790,7 @@ static void ich_read_data(uint8_t *data, int len) for (i = 0; i < len; i++) { if ((i % 4) == 0) - temp32 = readl_(g_cntlr.data + i); + temp32 = readl_(cntlr.data + i); data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; } @@ -812,20 +812,20 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, } /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); while (len > 0) { - block_len = min(len, g_cntlr.databytes); + block_len = min(len, cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; ich_hwseq_set_addr(addr); - hsfc = readw_(&g_cntlr.ich9_spi->hsfc); + hsfc = readw_(&cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &g_cntlr.ich9_spi->hsfc); + writew_(hsfc, &cntlr.ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) return 1; @@ -857,11 +857,11 @@ static void ich_fill_data(const uint8_t *data, int len) temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ - writel_(temp32, g_cntlr.data + (i - (i % 4))); + writel_(temp32, cntlr.data + (i - (i % 4))); } i--; if ((i % 4) != 3) /* Write remaining data to regs. */ - writel_(temp32, g_cntlr.data + (i - (i % 4))); + writel_(temp32, cntlr.data + (i - (i % 4))); } static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, @@ -880,24 +880,24 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, } /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); while (len > 0) { - block_len = min(len, g_cntlr.databytes); + block_len = min(len, cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; ich_hwseq_set_addr(addr); ich_fill_data(buf, block_len); - hsfc = readw_(&g_cntlr.ich9_spi->hsfc); + hsfc = readw_(&cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &g_cntlr.ich9_spi->hsfc); + writew_(hsfc, &cntlr.ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) { printk(BIOS_ERR, "SF: write failure at %x\n", @@ -934,7 +934,7 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, flash->name = "Opaque HW-sequencing"; ich_hwseq_set_addr(0); - switch ((g_cntlr.hsfs >> 3) & 3) { + switch ((cntlr.hsfs >> 3) & 3) { case 0: flash->sector_size = 256; break; @@ -949,12 +949,12 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, break; } - flash->size = 1 << (19 + (g_cntlr.flcomp & 7)); + flash->size = 1 << (19 + (cntlr.flcomp & 7)); flash->ops = &spi_flash_ops; - if ((g_cntlr.hsfs & HSFS_FDV) && ((g_cntlr.flmap0 >> 8) & 3)) - flash->size += 1 << (19 + ((g_cntlr.flcomp >> 3) & 7)); + if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3)) + flash->size += 1 << (19 + ((cntlr.flcomp >> 3) & 7)); printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); return 0; @@ -1008,16 +1008,16 @@ static int spi_flash_protect(const struct spi_flash *flash, int fpr; uint32_t *fpr_base; - fpr_base = g_cntlr.fpr; + fpr_base = cntlr.fpr; /* Find first empty FPR */ - for (fpr = 0; fpr < g_cntlr.fpr_max; fpr++) { + for (fpr = 0; fpr < cntlr.fpr_max; fpr++) { reg = read32(&fpr_base[fpr]); if (reg == 0) break; } - if (fpr == g_cntlr.fpr_max) { + if (fpr == cntlr.fpr_max) { printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); return -1; } @@ -1106,12 +1106,12 @@ void spi_finalize_ops(void) spi_opprefix = spi_config->opprefixes[0] | (spi_config->opprefixes[1] << 8); - writew_(spi_opprefix, g_cntlr.preop); + writew_(spi_opprefix, cntlr.preop); for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) { optype |= (spi_config->ops[i].type & 3) << (i * 2); - writeb_(spi_config->ops[i].op, &g_cntlr.opmenu[i]); + writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]); } - writew_(optype, g_cntlr.optype); + writew_(optype, cntlr.optype); } __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) -- cgit v1.2.3