From c16e9dfa18cb37b40ef7eef87f22385215b04ec2 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Fri, 29 May 2015 16:18:01 +0200 Subject: Create i945-ivy smm tseg init based on ivy code. CPU-side logic is unchanged for this range of CPUs as long as all of them use TSEG (or ASEG, just needs to be consistent). So uplift 206ax code while extracting southbridge and APIC code into separate functions. Change-Id: Ib365681d1da8115922c557fddcc59afc156826da Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/10465 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Alexandru Gagniuc --- src/southbridge/intel/bd82x6x/pch.h | 5 ----- src/southbridge/intel/bd82x6x/smi.c | 1 + 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 950dbc4fd8..3ce5d63bac 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -66,11 +66,6 @@ void intel_pch_finalize_smm(void); #include "chip.h" void pch_enable(device_t dev); #endif -/* These helpers are for performing SMM relocation. */ -void southbridge_smm_init(void); -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); - int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index 1768463065..d9c0e08c78 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "pch.h" /* While we read PMBASE dynamically in case it changed, let's -- cgit v1.2.3