From bf30ae63a9cf747aea8eebc7568d404e8b132c75 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Wed, 29 Oct 2014 08:58:28 +1100 Subject: intel/bd82x6x: Add new current for native USB ports Change-Id: I88ef36b94b961a318d280d8de1b8721fcbeb93b0 Signed-off-by: Damien Zammit Reviewed-on: http://review.coreboot.org/7237 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/southbridge/intel/bd82x6x/early_usb_native.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c index 7ce55742e5..b1f84471c0 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_native.c +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -33,7 +33,7 @@ early_usb_init (const struct southbridge_usb_port *portmap) /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; - const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 , 0x2000094a }; + const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 , 0x2000094a, 0x2000035f }; int i; /* Activate PMBAR. */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); -- cgit v1.2.3