From b50b6a5fa7e3d1810ab60dcc9b646ab7914b79e3 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 20 Aug 2020 16:50:01 +0200 Subject: nb/intel/sandybridge: Add x86_64 support Fix compilation on x86_64 by using compatible types. The MRC blob isn't supported yet as there's no x86_32 wrapper. Tested on HP8200: * Still boots on x86_32. * Boots to payload in x86_64 Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/44677 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/southbridge/intel/bd82x6x/azalia.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 24 ++++++++++++------------ src/southbridge/intel/bd82x6x/sata.c | 2 +- 3 files changed, 14 insertions(+), 14 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index dcb0bb40f0..1f14c422a8 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -165,7 +165,7 @@ static void azalia_init(struct device *dev) // NOTE this will break as soon as the Azalia get's a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); if (RCBA32(CIR31) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c6b42ea409..cc2eb28720 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -258,18 +258,18 @@ static void cpt_pm_init(struct device *dev) { printk(BIOS_DEBUG, "CougarPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); - RCBA32_AND_OR(CIR30, ~0UL, (1 << 6)|(1 << 0)); - RCBA32_AND_OR(CIR5, ~0UL, (1 << 0)); - RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14)); - RCBA16_AND_OR(CIR2, ~0UL, (1 << 14)); + RCBA32_AND_OR(CIR30, ~0U, (1 << 6)|(1 << 0)); + RCBA32_AND_OR(CIR5, ~0U, (1 << 0)); + RCBA16_AND_OR(CIR3, ~0U, (1 << 13)|(1 << 14)); + RCBA16_AND_OR(CIR2, ~0U, (1 << 14)); RCBA32(DMC) = 0xc0388400; - RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1)); + RCBA32_AND_OR(CIR6, ~0U, (1 << 5)|(1 << 18)); + RCBA32_AND_OR(CIR9, ~0U, (1 << 15)|(1 << 1)); RCBA32_AND_OR(CIR7, ~0x1f, 0xf); RCBA32(PM_CFG) = 0x050f0000; RCBA32(CIR8) = 0x04000000; - RCBA32_AND_OR(CIR10, ~0UL, 0xfffff); - RCBA32_AND_OR(CIR11, ~0UL, (1 << 1)); + RCBA32_AND_OR(CIR10, ~0U, 0xfffff); + RCBA32_AND_OR(CIR11, ~0U, (1 << 1)); RCBA32(CIR12) = 0x0001c000; RCBA32(CIR14) = 0x00061100; RCBA32(CIR15) = 0x7f8fdfff; @@ -371,10 +371,10 @@ static void enable_clock_gating(struct device *dev) reg16 |= (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); - pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + pch_iobp_update(0xEB007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEB004000, ~0U, (1 << 7)); + pch_iobp_update(0xEC007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEC004000, ~0U, (1 << 7)); reg32 = RCBA32(CG); reg32 |= (1 << 31); diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index c9bc14c123..08a254f3ec 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -126,7 +126,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); /* Initialize AHCI memory-mapped space */ - abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); -- cgit v1.2.3