From b0f81518b5c17466bc95ebdef292e82c4b76bc88 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 25 Jul 2016 21:31:41 -0500 Subject: chromeos mainboards: remove chromeos.asl Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh Reviewed-by: Duncan Laurie --- src/southbridge/intel/bd82x6x/pch.h | 6 ++++++ src/southbridge/intel/lynxpoint/pch.h | 2 ++ 2 files changed, 8 insertions(+) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 28323aca8f..f22fed59c3 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -51,6 +51,12 @@ #define DEFAULT_RCBA 0xfed1c000 #endif +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) +#define CROS_GPIO_DEVICE_NAME "CougarPoint" +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) +#define CROS_GPIO_DEVICE_NAME "PantherPoint" +#endif + #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a3cd811c7a..8cae50a949 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -19,6 +19,8 @@ #include +#define CROS_GPIO_DEVICE_NAME "LynxPoint" + /* * Lynx Point PCH PCI Devices: * -- cgit v1.2.3