From 976200388b6924c7b30c6062b64a8db7e215f37f Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Fri, 15 Sep 2017 15:19:32 -0600
Subject: southbridge/intel/bd82x6x: refactor rtc failure checking

In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to early_pch_common.c and
add a helper function to determine if failure occurred.

BUG=b:63054105

Change-Id: I710d99551cfb6455244f66b47fcbecc790ae770f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/southbridge/intel/bd82x6x/Makefile.inc       |  2 +-
 src/southbridge/intel/bd82x6x/early_pch_common.c | 14 ++++++++++++++
 src/southbridge/intel/bd82x6x/lpc.c              | 14 +++++---------
 src/southbridge/intel/bd82x6x/pch.h              |  3 +++
 4 files changed, 23 insertions(+), 10 deletions(-)

(limited to 'src/southbridge/intel')

diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index a570640f2e..8e882681ce 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -52,6 +52,6 @@ else
 romstage-y += early_me_mrc.c early_usb_mrc.c
 endif
 
-ramstage-y += madt.c
+ramstage-y += madt.c early_pch_common.c
 
 endif
diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c
index d2789005f0..0ea3dff001 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_common.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_common.c
@@ -17,10 +17,13 @@
 #include <arch/io.h>
 #include <timestamp.h>
 #include <cpu/x86/tsc.h>
+#include <device/pci_def.h>
 #include "pch.h"
 #include <arch/acpi.h>
 #include <console/console.h>
+#include <rules.h>
 
+#if ENV_ROMSTAGE
 uint64_t get_initial_timestamp(void)
 {
 	tsc_t base_time = {
@@ -56,3 +59,14 @@ int southbridge_detect_s3_resume(void)
 
 	return 0;
 }
+#endif
+
+int rtc_failure(void)
+{
+#if defined(__SIMPLE_DEVICE__)
+	device_t dev = PCI_DEV(0, 0x1f, 0);
+#else
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+#endif
+	return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD);
+}
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 3f722192e5..2bfc1e3374 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -277,18 +277,14 @@ static void pch_power_options(device_t dev)
 
 static void pch_rtc_init(struct device *dev)
 {
-	u8 reg8;
-	int rtc_failed;
+	int rtc_failed = rtc_failure();
 
-	reg8 = pci_read_config8(dev, GEN_PMCON_3);
-	rtc_failed = reg8 & RTC_BATTERY_DEAD;
 	if (rtc_failed) {
-		reg8 &= ~RTC_BATTERY_DEAD;
-		pci_write_config8(dev, GEN_PMCON_3, reg8);
-#if IS_ENABLED(CONFIG_ELOG)
-		elog_add_event(ELOG_TYPE_RTC_RESET);
-#endif
+		if (IS_ENABLED(CONFIG_ELOG))
+			elog_add_event(ELOG_TYPE_RTC_RESET);
+		pci_update_config8(dev, GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0);
 	}
+
 	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 
 	cmos_init(rtc_failed);
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index dcd7b2e130..51f3b94239 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -103,6 +103,9 @@ void
 early_usb_init (const struct southbridge_usb_port *portmap);
 
 #endif
+
+/* Return non-zero when RTC failure happened. */
+int rtc_failure(void);
 #endif
 
 #define MAINBOARD_POWER_OFF	0
-- 
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