From 8d783b84930e2e14e4f70234ea6589acd06557e7 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 14 May 2013 11:16:34 -0700 Subject: slippy: Minor vboot related fixes - Disable EC software sync for now - Report correct EC active firmware mode - Force enable developer mode by default - Set up PCH generic decode regions in romstage - Pass the oprom_is_loaded flag into vboot handoff data Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/51155 Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4169 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/southbridge/intel/lynxpoint/early_pch.c | 22 +++++++++++++++++++--- src/southbridge/intel/lynxpoint/lpc.c | 20 +------------------- 2 files changed, 20 insertions(+), 22 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 7a24e1fb03..38506c9438 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -20,10 +20,12 @@ #include #include +#include #include #include #include #include "pch.h" +#include "chip.h" #if CONFIG_INTEL_LYNXPOINT_LP #include "lp_gpio.h" @@ -96,15 +98,29 @@ static int sleep_type_s3(void) static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + const struct southbridge_intel_lynxpoint_config *config = NULL; /* Set COM1/COM2 decode range */ - pci_write_config16(dev, LPC_IO_DEC, 0x0010); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); + pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config); + + /* Set up generic decode ranges */ + if (!dev) + return; + if (dev->chip_info) + config = dev->chip_info; + if (!config) + return; + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); } int early_pch_init(const void *gpio_map, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index c3b5322190..33d74f1903 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -520,18 +520,6 @@ static void pch_fixups(struct device *dev) RCBA32_OR(0x21a8, 0x3); } -static void pch_decode_init(struct device *dev) -{ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "pch_decode_init\n"); - - pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); -} - static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n"); @@ -712,12 +700,6 @@ static void pch_lpc_read_resources(device_t dev) memset(gnvs, 0, sizeof(global_nvs_t)); } -static void pch_lpc_enable_resources(device_t dev) -{ - pch_decode_init(dev); - return pci_dev_enable_resources(dev); -} - static void pch_lpc_enable(device_t dev) { /* Enable PCH Display Port */ @@ -745,7 +727,7 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pch_lpc_enable_resources, + .enable_resources = pci_dev_enable_resources, .init = lpc_init, .enable = pch_lpc_enable, .scan_bus = scan_static_bus, -- cgit v1.2.3