From 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 1 Mar 2018 13:28:02 +0100 Subject: sb/intel/common: Fix conflicting OIC register definition Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location) makes some platforms use the wrong OIC register defi- nition. It was extended to 16-bit in the corporate version of ICH10. So let's give the new size and location a new name: EOIC (extended OIC). This only touches the systems affected by the mentioned change. Other platforms still need to be adapted before they can use the common RCBA definitions. Change-Id: If9e554c072f01412164dc35e0b09272142e3796f Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/24924 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Reviewed-by: Bill XIE Reviewed-by: Arthur Heymans --- src/southbridge/intel/bd82x6x/early_rcba.c | 4 ++-- src/southbridge/intel/common/rcba.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 990ff0d874..9ce9dc9d41 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -60,9 +60,9 @@ southbridge_configure_default_intmap(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; + RCBA16(EOIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void) RCBA16(EOIC); } void diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index 1399fdef90..ad8285a500 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -147,6 +147,7 @@ #define D20IR 0x3160 /* 16bit */ #define D19IR 0x3168 /* 16bit */ +#define EOIC 0x31fe /* 16bit */ #define OIC 0x31ff /* 8bit */ #define DIR_ROUTE(x, a, b, c, d) \ -- cgit v1.2.3