From 7843bd560e65b0a83e99b42bdd58dd6363656c56 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 21:56:37 +0100 Subject: nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801jx/Kconfig | 5 ----- src/southbridge/intel/i82801jx/Makefile.inc | 3 +++ src/southbridge/intel/i82801jx/bootblock.c | 9 +++++---- src/southbridge/intel/i82801jx/early_init.c | 2 +- src/southbridge/intel/i82801jx/i82801jx.h | 1 + 5 files changed, 10 insertions(+), 10 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index eeb843e910..7f44fcfc1d 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -51,9 +51,4 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED config HPET_MIN_TICKS hex default 0x80 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801jx/bootblock.c" - endif diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 30ed351970..1527b8adb0 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -16,6 +16,9 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y) +bootblock-y += bootblock.c +bootblock-y += early_init.c + ramstage-y += i82801jx.c ramstage-y += pci.c ramstage-y += lpc.c diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 01faef34af..b6016793c2 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -14,6 +14,7 @@ */ #include +#include #include "i82801jx.h" static void enable_spi_prefetch(void) @@ -29,14 +30,14 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, 0xdc, reg8); } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); - /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, - (uintptr_t)DEFAULT_RCBA | 1); + i82801jx_setup_bars(); /* Enable upper 128bytes of CMOS. */ RCBA32(0x3400) = (1 << 2); + + i82801jx_lpc_setup(); } diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 469073240e..1afc6b365f 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -56,7 +56,7 @@ void i82801jx_lpc_setup(void) pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); } -static void i82801jx_setup_bars(void) +void i82801jx_setup_bars(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index d406d1d631..26a99f42f7 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -235,6 +235,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); #endif void i82801jx_lpc_setup(void); +void i82801jx_setup_bars(void); void i82801jx_early_init(void); #endif -- cgit v1.2.3