From 6ef23316c235d14213d0bdc48c6853d3059a0b64 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 8 Sep 2021 15:06:56 +0200 Subject: sb/intel/lynxpoint/pcie.c: Fix 0xf5 register mask Lynx Point PCH reference code version 1.9.1 masks the upper 4 bits of the PCIe root port register at offset 0xf5. Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/57502 Reviewed-by: Lean Sheng Tan Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index fd41ce8936..30a34f757a 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -662,7 +662,7 @@ static void pch_pcie_early(struct device *dev) /* Set Invalid Receive Range Check Enable in MPC register. */ pci_or_config32(dev, 0xd8, 1 << 25); - pci_and_config8(dev, 0xf5, 0x3f); + pci_and_config8(dev, 0xf5, 0x0f); if (rp == 1 || rp == 5 || (is_lp && rp == 6)) pci_and_config8(dev, 0xf7, ~0x0c); -- cgit v1.2.3