From 61f902d4a7779d0ce30de79df7a71ad0c3788887 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Sat, 7 Jun 2014 16:41:14 +0200 Subject: ibexpeak: Set number of USB ports. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ife3febcc88967386dfae624cd237562a34a68471 Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/5956 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/ibexpeak/usb_ehci.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 21a257f328..868a06843c 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -30,6 +30,8 @@ static void usb_ehci_init(struct device *dev) { u32 reg32; + struct resource *res; + u8 access_cntl; /* Disable Wake on Disconnect in RMH */ reg32 = RCBA32(0x35b0); @@ -50,6 +52,21 @@ static void usb_ehci_init(struct device *dev) //reg32 |= PCI_COMMAND_SERR; pci_write_config32(dev, PCI_COMMAND, reg32); + access_cntl = pci_read_config8(dev, 0x80); + + /* Enable writes to protected registers. */ + pci_write_config8(dev, 0x80, access_cntl | 1); + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + /* Number of ports and companion controllers. */ + reg32 = read32(res->base + 4); + write32(res->base + 4, (reg32 & 0xfff00000) | 2); + } + + /* Restore protection. */ + pci_write_config8(dev, 0x80, access_cntl); + printk(BIOS_DEBUG, "done.\n"); } -- cgit v1.2.3