From 58649b058baecf24a07a2bc85fff68b339d67503 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 5 Apr 2015 18:03:15 -0500 Subject: src/southbridge/intel/i82801ix: Add GPIO register locations Change-Id: I226a1a6bc6b1f921c03f8ec57875a88314928aeb Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/9318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/southbridge/intel/i82801ix/i82801ix.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 10b27179ca..afc644b4a7 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * Copyright (C) 2008-2009 coresystems GmbH * 2012 secunet Security Networks AG * @@ -76,6 +77,15 @@ #define ALT_GP_SMI_STS 0x3a +#define GP_IO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GP_IO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 + #define DEBUG_PERIODIC_SMIS 0 #define MAINBOARD_POWER_OFF 0 -- cgit v1.2.3