From 490473edec3817902c0fff0d6635ac9bbb58bac2 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 21 Jun 2020 17:10:28 +0200
Subject: sb/intel/i82801jx: Use pmutil.h definitions

Also drop now-redundant definitions and include headers where needed.

Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical.

Change-Id: I2fb46bb04d96df5e8261f49e0fd4d88eedca6084
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42659
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/i82801jx/early_init.c |  1 +
 src/southbridge/intel/i82801jx/i82801jx.h   | 33 -----------------------------
 src/southbridge/intel/i82801jx/lpc.c        |  1 +
 3 files changed, 2 insertions(+), 33 deletions(-)

(limited to 'src/southbridge/intel')

diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c
index 8ed7a41784..bfc5ca9b10 100644
--- a/src/southbridge/intel/i82801jx/early_init.c
+++ b/src/southbridge/intel/i82801jx/early_init.c
@@ -5,6 +5,7 @@
 #include <device/smbus_host.h>
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmbase.h>
+#include <southbridge/intel/common/pmutil.h>
 #include "i82801jx.h"
 #include "chip.h"
 
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 6559f8fb41..a88c19ed2f 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -14,30 +14,6 @@
 
 #define APM_CNT		0xb2
 
-#define PM1_STS		0x00
-#define   PWRBTN_STS	(1 <<  8)
-#define   RTC_STS	(1 << 10)
-#define PM1_EN		0x02
-#define   PWRBTN_EN	(1 <<  8)
-#define   GBL_EN	(1 <<  5)
-#define PM1_CNT		0x04
-#define   SCI_EN	(1 << 0)
-#define PM_LV2		0x14
-#define PM_LV3		0x15
-#define PM_LV4		0x16
-#define PM_LV5		0x17
-#define PM_LV6		0x18
-#define GPE0_STS	0x20
-#define SMI_EN		0x30
-#define   PERIODIC_EN	(1 << 14)
-#define   TCO_EN	(1 << 13)
-#define   APMC_EN	(1 <<  5)
-#define   BIOS_EN	(1 <<  2)
-#define   EOS		(1 <<  1)
-#define   GBL_SMI_EN	(1 <<  0)
-#define SMI_STS		0x34
-#define ALT_GP_SMI_EN	0x38
-#define ALT_GP_SMI_STS	0x3a
 
 
 #define GP_IO_USE_SEL	0x00
@@ -56,8 +32,6 @@
 #define MAINBOARD_POWER_KEEP	2
 
 /* D31:F0 LPC bridge */
-#define D31F0_PMBASE		0x40
-#define PMBASE		D31F0_PMBASE
 #define D31F0_ACPI_CNTL		0x44
 #define ACPI_CNTL		D31F0_ACPI_CNTL
 #define D31F0_GPIO_BASE		0x48
@@ -87,18 +61,11 @@
 #define D31F0_GEN2_DEC		0x88
 #define D31F0_GEN3_DEC		0x8c
 #define D31F0_GEN4_DEC		0x90
-#define D31F0_GEN_PMCON_1	0xa0
-#define D31F0_GEN_PMCON_3	0xa4
 #define D31F0_C5_EXIT_TIMING	0xa8
 #define D31F0_CxSTATE_CNF	0xa9
 #define D31F0_C4TIMING_CNT	0xaa
 #define D31F0_GPIO_ROUT		0xb8
 
-/* GEN_PMCON_3 bits */
-#define RTC_BATTERY_DEAD	(1 << 2)
-#define RTC_POWER_FAILED	(1 << 1)
-#define SLEEP_AFTER_POWER_FAIL	(1 << 0)
-
 
 /* D31:F2 SATA */
 #define D31F2_IDE_TIM_PRI	0x40
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index 815a205dd0..c36009ed0a 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -21,6 +21,7 @@
 #include "i82801jx.h"
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>
+#include <southbridge/intel/common/pmutil.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
 
 #define NMI_OFF	0
-- 
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