From 3dc12c1e19181bb9bacebeda706c39cfb57eb326 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Wed, 17 Sep 2014 02:38:51 +0200 Subject: bd82x6x: Consolidate early native USB init Change-Id: I6189930fd3c69c3497e4cf1a78035e6614761b13 Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/6923 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/southbridge/intel/bd82x6x/Makefile.inc | 10 +-- src/southbridge/intel/bd82x6x/early_usb_native.c | 77 ++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/pch.h | 11 ++++ 3 files changed, 93 insertions(+), 5 deletions(-) create mode 100644 src/southbridge/intel/bd82x6x/early_usb_native.c (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index b79b85a0a9..3d33edcd13 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -47,14 +47,14 @@ smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c -romstage-y += early_usb.c early_smbus.c me_status.c gpio.c +romstage-y += early_smbus.c me_status.c gpio.c romstage-y += reset.c romstage-y += early_spi.c early_pch.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c early_usb.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c early_usb.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) IFD_BIN_PATH := $(objgenerated)/ifdfake.bin diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c new file mode 100644 index 0000000000..2afe8d3cf7 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE. */ +#include "pch.h" + +void +early_usb_init (const struct southbridge_usb_port *portmap) +{ + u32 reg32; + const u32 rcba_dump[8] = { + /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, + /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, + }; + const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 }; + int i; + /* Activate PMBAR. */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + + /* Unlock registers. */ + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + for (i = 0; i < 14; i++) + write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), + currents[portmap[i].current]); + for (i = 0; i < 10; i++) + write32 (DEFAULT_RCBABASE | (0x3538 + 4 * i), 0); + + for (i = 0; i < 8; i++) + write32 (DEFAULT_RCBABASE | (0x3560 + 4 * i), rcba_dump[i]); + for (i = 0; i < 8; i++) + write32 (DEFAULT_RCBABASE | (0x3580 + 4 * i), 0); + reg32 = 0; + for (i = 0; i < 14; i++) + if (!portmap[i].enabled) + reg32 |= (1 << i); + write32 (DEFAULT_RCBABASE | 0x359c, reg32); + reg32 = 0; + for (i = 0; i < 8; i++) + if (portmap[i].enabled && portmap[i].oc_pin >= 0) + reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); + write32 (DEFAULT_RCBABASE | 0x35a0, reg32); + reg32 = 0; + for (i = 8; i < 14; i++) + if (portmap[i].enabled && portmap[i].oc_pin >= 4) + reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); + write32 (DEFAULT_RCBABASE | 0x35a4, reg32); + for (i = 0; i < 22; i++) + write32 (DEFAULT_RCBABASE | (0x35a8 + 4 * i), 0); + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + /* Relock registers. */ + outw (0x0000, DEFAULT_PMBASE | 0x003c); +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index aabf617d3a..7a796df091 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -77,6 +77,17 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); void early_pch_init_native(void); int southbridge_detect_s3_resume(void); + +struct southbridge_usb_port +{ + int enabled; + int current; + int oc_pin; +}; + +void +early_usb_init (const struct southbridge_usb_port *portmap); + #endif #endif -- cgit v1.2.3