From 21d6a27ac07d5233a7dd473d84c4c0b541059146 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 5 Nov 2019 18:50:38 +0200 Subject: arch/x86: Replace some __SMM__ guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We generally do not guard source in attempts to reduce the final object sizes, but rely on garbage collection. Most of the __unused attributes inserted here will be removed when remaining __SIMPLE_DEVICE__ guards can be removed. Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36641 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/southbridge/intel/bd82x6x/me.c | 25 ++++++++++--------------- src/southbridge/intel/bd82x6x/me_8.x.c | 27 +++++++++++---------------- src/southbridge/intel/bd82x6x/pch.c | 7 ++----- src/southbridge/intel/common/gpio.c | 2 +- src/southbridge/intel/common/pmbase.c | 2 +- src/southbridge/intel/ibexpeak/me.c | 28 ++++++++++++---------------- src/southbridge/intel/lynxpoint/me_9.x.c | 26 ++++++++++++++++---------- src/southbridge/intel/lynxpoint/pch.c | 4 ++-- src/southbridge/intel/lynxpoint/usb_ehci.c | 6 +++--- src/southbridge/intel/lynxpoint/usb_xhci.c | 6 +++--- 10 files changed, 61 insertions(+), 72 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 8adb95bdb3..15f99cdf78 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include #include #include @@ -33,11 +35,6 @@ #include #include -#ifndef __SMM__ -#include -#include -#endif - #include "me.h" #include "pch.h" @@ -45,9 +42,8 @@ #include #endif -#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -55,7 +51,6 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -#endif /* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -112,7 +107,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); @@ -346,9 +341,8 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, return 0; } -#ifdef __SMM__ /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -370,7 +364,6 @@ static int mkhi_end_of_post(void) printk(BIOS_INFO, "ME: END OF POST message successful\n"); return 0; } -#endif /* Get ME firmware version */ static int __unused mkhi_get_fw_version(void) @@ -486,7 +479,8 @@ int mkhi_global_reset(void) } #endif -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ + static void intel_me7_finalize_smm(void) { struct me_hfs hfs; @@ -536,7 +530,8 @@ void intel_me_finalize_smm(void) printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); } } -#else /* !__SMM__ */ + +#else /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -748,4 +743,4 @@ static const struct pci_driver intel_me __pci_driver = { .device = 0x1c3a, }; -#endif /* !__SMM__ */ +#endif /* __SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 7af969517d..f13ced939a 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -24,6 +24,8 @@ #include #include +#include +#include #include #include #include @@ -33,11 +35,6 @@ #include #include -#ifndef __SMM__ -#include -#include -#endif - #include "me.h" #include "pch.h" @@ -46,9 +43,8 @@ #include #endif -#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -57,7 +53,6 @@ static const char *me_bios_path_values[] = { [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; static int intel_me_read_mbp(me_bios_payload *mbp_data); -#endif /* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -115,7 +110,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); @@ -453,10 +448,8 @@ static int mkhi_global_reset(void) } #endif -#ifdef __SMM__ - /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -482,6 +475,8 @@ static int mkhi_end_of_post(void) return 0; } +#ifdef __SIMPLE_DEVICE__ + void intel_me8_finalize_smm(void) { struct me_hfs hfs; @@ -517,7 +512,7 @@ void intel_me8_finalize_smm(void) RCBA32_OR(FD2, PCH_DISABLE_MEI1); } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -752,6 +747,8 @@ static const struct pci_driver intel_me __pci_driver = { .device = 0x1e3a, }; +#endif /* !__SIMPLE_DEVICE__ */ + /****************************************************************************** * */ static u32 me_to_host_words_pending(void) @@ -783,7 +780,7 @@ static u32 host_to_me_words_room(void) * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data) +static int __unused intel_me_read_mbp(me_bios_payload *mbp_data) { mbp_header mbp_hdr; mbp_item_header mbp_item_hdr; @@ -907,5 +904,3 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) return 0; } - -#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index de7fc36ef6..3cd39a6706 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -17,12 +17,9 @@ #include #include -#ifdef __SMM__ -#include -#else /* !__SMM__ */ #include #include -#endif +#include #include #include @@ -145,7 +142,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) return; } -#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ /* Set bit in function disable register to hide this device */ static void pch_hide_devfn(unsigned int devfn) { diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 0669b5fcca..9731d75086 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -35,7 +35,7 @@ static u16 get_gpio_base(void) { -#if defined(__SMM__) +#ifdef __SIMPLE_DEVICE__ /* Don't assume GPIO_BASE is still the same */ return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; #else diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index ae13272026..ff0410adba 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -38,7 +38,7 @@ u16 lpc_get_pmbase(void) { -#if defined(__SMM__) +#ifdef __SIMPLE_DEVICE__ /* Don't assume PMBASE is still the same */ return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc; #else diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 6aa33cad90..63dff6ace8 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -23,20 +23,17 @@ */ #include -#include -#include #include -#include +#include +#include +#include #include +#include +#include #include #include #include -#ifndef __SMM__ -#include -#include -#endif - #include "me.h" #include "pch.h" @@ -44,9 +41,8 @@ #include #endif -#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -54,7 +50,6 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -#endif /* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -111,7 +106,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev,void *ptr, int offset) { @@ -131,7 +126,6 @@ static inline void write_host_csr(struct mei_csr *csr) mei_write_dword_ptr(csr, MEI_H_CSR); } -#ifdef __SMM__ static inline void read_me_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_ME_CSR_HA); @@ -348,7 +342,7 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, } /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -371,6 +365,8 @@ static int mkhi_end_of_post(void) return 0; } +#ifdef __SIMPLE_DEVICE__ + static void intel_me7_finalize_smm(void) { struct me_hfs hfs; @@ -420,7 +416,7 @@ void intel_me_finalize_smm(void) printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); } } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -629,4 +625,4 @@ static const struct pci_driver intel_me __pci_driver = { .devices = pci_device_ids }; -#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 429fa42ab1..2df03c9cdc 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -45,9 +45,8 @@ #include #endif -#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -56,7 +55,6 @@ static const char *me_bios_path_values[] = { [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); -#endif /* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -557,10 +555,8 @@ static int mkhi_global_reset(void) } #endif -#ifdef __SMM__ - /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -579,6 +575,8 @@ static int mkhi_end_of_post(void) return 0; } +#ifdef __SIMPLE_DEVICE__ + void intel_me_finalize_smm(void) { struct me_hfs hfs; @@ -619,7 +617,7 @@ void intel_me_finalize_smm(void) RCBA32_OR(FD2, PCH_DISABLE_MEI1); } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ static inline int mei_sendrecv_icc(struct icc_header *icc, void *req_data, int req_bytes, @@ -901,6 +899,8 @@ static const struct pci_driver intel_me __pci_driver = { .devices= pci_device_ids, }; +#endif /* !__SIMPLE_DEVICE__ */ + /****************************************************************************** * */ static u32 me_to_host_words_pending(void) @@ -938,7 +938,7 @@ struct mbp_payload { * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) +static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; @@ -947,7 +947,11 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) struct mbp_payload *mbp; int i; +#ifdef __SIMPLE_DEVICE__ + pci_read_dword_ptr(PCI_BDF(dev), &hfs2, PCI_ME_HFS2); +#else pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); +#endif if (!hfs2.mbp_rdy) { printk(BIOS_ERR, "ME: MBP not ready\n"); @@ -1057,8 +1061,10 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) return 0; mbp_failure: +#ifdef __SIMPLE_DEVICE__ + intel_me_mbp_give_up(PCI_BDF(dev)); +#else intel_me_mbp_give_up(dev); +#endif return -1; } - -#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index dc7b9580d9..cb50c125ec 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -90,7 +90,7 @@ u16 get_gpiobase(void) return gpiobase; } -#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ /* Put device in D3Hot Power State */ static void pch_enable_d3hot(struct device *dev) @@ -330,4 +330,4 @@ struct chip_operations southbridge_intel_lynxpoint_ops = { .enable_dev = pch_enable, }; -#endif /* __SMM__ */ +#endif /* __SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index bc86053eca..3e50beeb09 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -24,7 +24,7 @@ #include #include "pch.h" -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ void usb_ehci_disable(pci_devfn_t dev) { @@ -132,7 +132,7 @@ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) } } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ static void usb_ehci_clock_gating(struct device *dev) { @@ -202,4 +202,4 @@ static const struct pci_driver pch_usb_ehci __pci_driver = { .devices = pci_device_ids, }; -#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 686e06a6a9..4818d626f0 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -166,7 +166,7 @@ static void usb_xhci_reset_usb3(struct device *dev, int all) usb_xhci_reset_status_usb3(mem_base, port); } -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ /* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) @@ -251,7 +251,7 @@ void usb_xhci_route_all(void) usb_xhci_reset_usb3(PCH_XHCI_DEV, 1); } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ static void usb_xhci_clock_gating(struct device *dev) { @@ -395,4 +395,4 @@ static const struct pci_driver pch_usb_xhci __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; -#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ -- cgit v1.2.3