From 1ad5564dd675a246f5b0a05d03482836d49d44a9 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 7 Mar 2013 14:08:04 -0800 Subject: lynxpoint: Add helper functions for reading PM and GPIO base These base addresses are used in several places and it is helpful to have one location that is reading it. Change-Id: Ibf589247f37771f06c18e3e58f92aaf3f0d11271 Signed-off-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/2812 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/southbridge/intel/lynxpoint/pch.c | 20 ++++++++++++++++++++ src/southbridge/intel/lynxpoint/pch.h | 3 ++- 2 files changed, 22 insertions(+), 1 deletion(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 6f03716283..b4f64e1436 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -65,6 +65,26 @@ int pch_is_lp(void) return pch_silicon_type() == PCH_TYPE_LPT_LP; } +u16 get_pmbase(void) +{ + static u16 pmbase; + + if (!pmbase) + pmbase = pci_read_config16(pch_get_lpc_device(), + PMBASE) & 0xfffc; + return pmbase; +} + +u16 get_gpiobase(void) +{ + static u16 gpiobase; + + if (!gpiobase) + gpiobase = pci_read_config16(pch_get_lpc_device(), + GPIOBASE) & 0xfffc; + return gpiobase; +} + #ifndef __SMM__ /* Set bit in Function Disble register to hide this device */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 38202b5690..db9bb776f7 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -130,7 +130,8 @@ void pch_config_rcba(const struct rcba_config_instruction *rcba_config); int pch_silicon_revision(void); int pch_silicon_type(void); int pch_is_lp(void); - +u16 get_pmbase(void); +u16 get_gpiobase(void); #if !defined(__PRE_RAM__) && !defined(__SMM__) #include #include -- cgit v1.2.3