From 1a1b04ea51686226e9dddbd9dd74550b340578a1 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 7 Jan 2020 22:34:33 +0200 Subject: device/smbus_host: Declare common early SMBus prototypes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/38233 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/bd82x6x/early_smbus.c | 5 ----- src/southbridge/intel/bd82x6x/pch.h | 4 ---- src/southbridge/intel/i82371eb/early_smbus.c | 5 ----- src/southbridge/intel/i82371eb/i82371eb.h | 4 ---- src/southbridge/intel/i82801dx/early_smbus.c | 5 ----- src/southbridge/intel/i82801dx/i82801dx.h | 2 -- src/southbridge/intel/i82801gx/early_smbus.c | 20 -------------------- src/southbridge/intel/i82801gx/i82801gx.h | 8 -------- src/southbridge/intel/i82801ix/early_smbus.c | 5 ----- src/southbridge/intel/i82801ix/i82801ix.h | 4 ---- src/southbridge/intel/i82801jx/early_smbus.c | 21 --------------------- src/southbridge/intel/i82801jx/i82801jx.h | 8 -------- src/southbridge/intel/ibexpeak/early_smbus.c | 20 -------------------- src/southbridge/intel/ibexpeak/pch.h | 7 ------- src/southbridge/intel/lynxpoint/early_smbus.c | 5 ----- src/southbridge/intel/lynxpoint/pch.h | 5 ----- 16 files changed, 128 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 3e94c150e6..7d8503bb7d 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -32,8 +32,3 @@ int smbus_enable_iobar(uintptr_t base) return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index a8c14c96bb..ed75505f65 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -48,10 +48,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index cbafd72519..97cf5fd7c0 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -44,8 +44,3 @@ int smbus_enable_iobar(uintptr_t base) return 0; } - -int smbus_read_byte(u8 device, u8 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index a08be0db14..e20cb5f1fb 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -8,10 +8,6 @@ void enable_pm(void); void i82371eb_early_init(void); -#if ENV_ROMSTAGE -int smbus_read_byte(u8 device, u8 address); -#endif - #endif /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 5cf203daed..6649c33b8b 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -28,8 +28,3 @@ int smbus_enable_iobar(uintptr_t base) return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 77e426971f..d5f09aa61f 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -16,11 +16,9 @@ #if !defined(__ASSEMBLER__) #include -#include "chip.h" void i82801dx_enable(struct device *dev); void i82801dx_early_init(void); -int smbus_read_byte(unsigned int device, unsigned int address); void aseg_smm_lock(void); #endif diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 4d4ecb18c5..48d9d58acc 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -30,23 +30,3 @@ int smbus_enable_iobar(uintptr_t base) return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) -{ - return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); -} - -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 71510a431a..fbb6bf1868 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -28,15 +28,7 @@ void i82801gx_lpc_setup(void); void i82801gx_setup_bars(void); void i82801gx_early_init(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, - u8 *buf); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf); void ich7_setup_cir(void); -#endif #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 556fe1a107..ba0b0c81f0 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -32,8 +32,3 @@ int smbus_enable_iobar(uintptr_t base) return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 6ff696bda8..58a49f1531 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -198,10 +198,6 @@ void i82801ix_lpc_decode(void); void i82801ix_dmi_setup(void); void i82801ix_dmi_poll_vc1(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - #endif #endif diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index 87b7ba5fbc..55b9854598 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -27,24 +27,3 @@ int smbus_enable_iobar(uintptr_t base) return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) -{ - return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); -} - -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 0c99d20f1d..842e049fdd 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -210,14 +210,6 @@ static inline int lpc_is_mobile(const u16 devid) } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, - u8 *buf); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf); -#endif void i82801jx_lpc_setup(void); void i82801jx_setup_bars(void); void i82801jx_early_init(void); diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index f340aef267..7d8503bb7d 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -32,23 +32,3 @@ int smbus_enable_iobar(uintptr_t base) return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -int smbus_write_byte(unsigned int device, unsigned int address, u8 data) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); -} - -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index a40fc64451..d0f131482b 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -39,13 +39,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int smbus_write_byte(unsigned int device, unsigned int address, u8 data); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); -#endif - void early_pch_init(void); void early_thermal_init(void); diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 3e94c150e6..7d8503bb7d 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -32,8 +32,3 @@ int smbus_enable_iobar(uintptr_t base) return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 19f8637ed6..093ebfaf7e 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -160,11 +160,6 @@ void pch_log_state(void); void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); - -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - void enable_usb_bar(void); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); -- cgit v1.2.3