From 0dd5e4395e805e3d54b31f3eaf8b432af5bad5e2 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Tue, 29 Jul 2014 22:35:45 +0200 Subject: i82801ix: Allow configuration of SATA mode in CMOS. Change-Id: Ice0f0273b16a946143c038a90b61978269c1c56e Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/6409 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Paul Menzel --- src/southbridge/intel/i82801ix/chip.h | 2 -- src/southbridge/intel/i82801ix/sata.c | 23 ++++++++++++++++------- 2 files changed, 16 insertions(+), 9 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 222cfb5095..5e1221d28b 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -70,8 +70,6 @@ struct southbridge_intel_i82801ix_config { uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; /* If enabled, keep bit 2 of sata_enabled unset. */ uint8_t sata_port_map : 6; int sata_clock_request : 1; int sata_traffic_monitor : 1; diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 02f6d5348b..10c8a2bd15 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -25,6 +25,7 @@ #include #include #include "i82801ix.h" +#include typedef struct southbridge_intel_i82801ix_config config_t; @@ -149,6 +150,7 @@ static void sata_init(struct device *const dev) const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID); const int is_mobile = (devid == 0x2928) || (devid == 0x2929); + u8 sata_mode; printk(BIOS_DEBUG, "i82801ix_sata: initializing...\n"); @@ -158,6 +160,10 @@ static void sata_init(struct device *const dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + /* Default to AHCI */ + sata_mode = 0; + /* * TODO: In contrast to ICH7 and PCH code we don't set * timings, dma and IDE-I/O settings here. Looks like they @@ -171,13 +177,11 @@ static void sata_init(struct device *const dev) PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | /* read-only in IDE modes */ PCI_COMMAND_IO); - if (!config->sata_ahci) + if (sata_mode != 0) /* No AHCI: clear AHCI base */ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); - } else if (config->sata_ahci) { + if (sata_mode == 0) { printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); } else { printk(BIOS_DEBUG, "SATA controller in native mode.\n"); @@ -193,7 +197,7 @@ static void sata_init(struct device *const dev) /* Port enable. For AHCI, it's managed in memory mapped space. */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; - reg16 |= (1 << 15) | (config->sata_ahci ? 0x3f : config->sata_port_map); + reg16 |= (1 << 15) | ((sata_mode == 0) ? 0x3f : config->sata_port_map); pci_write_config16(dev, 0x92, reg16); /* SATA clock settings */ @@ -218,7 +222,7 @@ static void sata_init(struct device *const dev) } } - if (config->sata_ahci) + if (sata_mode == 0) sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); sata_program_indexed(dev, is_mobile); @@ -230,15 +234,20 @@ static void sata_enable(device_t dev) const config_t *const config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + /* Default to AHCI */ + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0040 | 0x0020; /* SATA mode + all ports on D31:F2 */ map |= (config->sata_port_map ^ 0x3f) << 8; -- cgit v1.2.3