From d4ba2b14caf61a8a9716a6525b8e4313f6121e7b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 12 Oct 2021 21:01:13 +0200 Subject: sb/intel/lynxpoint: Enable PCIe Clock PM and ASPM L1 Enable PCIe Clock power management and ASPM L1 substate by default. This matches what Broadwell does. Change-Id: Ic2bbcbc23d6bab0900d3e90ad8e2fbfa4aea3c16 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58281 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/southbridge/intel/lynxpoint') diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 03b3e9a50f..25ed6efa12 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -68,6 +68,12 @@ config PCIEXP_AER bool default y +config PCIEXP_CLK_PM + default y + +config PCIEXP_L1_SUB_STATE + default y + config SERIALIO_UART_CONSOLE bool "Use SerialIO UART for console" depends on INTEL_LYNXPOINT_LP -- cgit v1.2.3