From 9ffb57c6781676d5d8f54e3dba59b01a60c53c2e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 13:48:46 +0100 Subject: sb/intel/lynxpoint: Relocate SATA clock gating write Do it in the same place as Broadwell. Tested on out-of-tree Compal LA-A992P, SATA still works. Change-Id: I50bd951af52d03ad986dbf4bf70bdae348fa994b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47034 Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/lpc.c | 2 -- src/southbridge/intel/lynxpoint/sata.c | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'src/southbridge/intel/lynxpoint') diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index fc287b0f80..fb421451f8 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -565,8 +565,6 @@ static void enable_lp_clock_gating(struct device *dev) RCBA32_OR(0x3434, 0x7); // LP LPC - RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA - RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic pch_iobp_update(0xCF000000, ~0, 0x00007001); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 2a356004aa..1b69b8099f 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -187,6 +187,7 @@ static void sata_init(struct device *dev) if (pch_is_lp()) { sir_write(dev, 0x54, 0xcf000f0f); sir_write(dev, 0x58, 0x00190000); + RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); } reg32 = pci_read_config32(dev, 0x300); -- cgit v1.2.3