From 6e732d34a0c1b87803925065b66076599c1e5642 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 28 Jan 2021 13:56:18 +0100 Subject: intel: Turn `DEFAULT_RCBA` into a Kconfig symbol Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases where a pointer cast would be necessary. Instances in Sandy Bridge MRC code were left as-is intentionally, so as not to collide with another cleanup patch train. Tested with BUILD_TIMELESS=1, these boards remain identical: - Asus P8Z77-V LX2 - Packard Bell MS2290 Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/acpi/pch.asl | 2 +- src/southbridge/intel/lynxpoint/bootblock.c | 2 +- src/southbridge/intel/lynxpoint/early_pch.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'src/southbridge/intel/lynxpoint') diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a878dc274d..f97a5ad58d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -19,7 +19,7 @@ Scope (\) } // Root Complex Register Block - OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 802c58ef88..c063bfb10a 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -7,7 +7,7 @@ static void map_rcba(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); } static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 8cc6a8760c..ace8b54552 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -36,7 +36,7 @@ enum pch_platform_type get_pch_platform_type(void) static void pch_enable_bars(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 24a5a7ef9a..20b9b4318f 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -557,9 +557,9 @@ static void pch_lpc_add_mmio_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* RCBA */ - if ((uintptr_t)DEFAULT_RCBA < default_decode_base) { + if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) { res = new_resource(dev, RCBA); - res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; + res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; -- cgit v1.2.3