From 63626b1a4a31588995ff6f0ba42952b6086cbded Mon Sep 17 00:00:00 2001 From: Tristan Corrick Date: Fri, 30 Nov 2018 22:53:50 +1300 Subject: sb/intel/common: Create a common PCH finalise implementation The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak. Lynx Point now benefits from being able to write-protect the flash chip. For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done in bd82x6x. Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is configured, flashrom reports all flash regions as read-only, and does not manage to alter the contents of the flash chip. Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to work as before. Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Signed-off-by: Tristan Corrick Reviewed-on: https://review.coreboot.org/c/29977 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/Kconfig | 1 + src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- src/southbridge/intel/lynxpoint/finalize.c | 68 ---------------------------- src/southbridge/intel/lynxpoint/lpc.c | 5 ++ src/southbridge/intel/lynxpoint/pch.h | 1 - src/southbridge/intel/lynxpoint/smihandler.c | 3 ++ 6 files changed, 10 insertions(+), 70 deletions(-) delete mode 100644 src/southbridge/intel/lynxpoint/finalize.c (limited to 'src/southbridge/intel/lynxpoint') diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5b06c4ba8e..b331ba1c77 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -25,6 +25,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT + select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select IOAPIC select HAVE_USBDEBUG_OPTIONS select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index db3454691f..c2a49fdea6 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -42,7 +42,7 @@ ramstage-y += acpi.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c pch.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c deleted file mode 100644 index 590a24513a..0000000000 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "me.h" -#include "pch.h" - -void intel_pch_finalize_smm(void) -{ - /* Lock down Management Engine */ - intel_me_finalize_smm(); - - /* Set SPI opcode menu */ - RCBA16(0x3894) = SPI_OPPREFIX; - RCBA16(0x3896) = SPI_OPTYPE; - RCBA32(0x3898) = SPI_OPMENU_LOWER; - RCBA32(0x389c) = SPI_OPMENU_UPPER; - - /* Lock SPIBAR */ - RCBA32_OR(0x3804, (1 << 15)); - -#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) - /* Re-init SPI driver to handle locked BAR */ - spi_init(); -#endif - - /* TCLOCKDN: TC Lockdown */ - RCBA32_OR(0x0050, (1UL << 31)); - - /* BIOS Interface Lockdown */ - RCBA32_OR(0x3410, (1 << 0)); - - /* Function Disable SUS Well Lockdown */ - RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); - - /* Global SMI Lock */ - pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); - - /* GEN_PMCON Lock */ - pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); - - /* PMSYNC */ - RCBA32_OR(PMSYNC_CONFIG, (1UL << 31)); - - /* R/WO registers */ - RCBA32(0x21a4) = RCBA32(0x21a4); - pci_write_config32(PCI_DEV(0, 27, 0), 0x74, - pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); - - /* Indicate finalize step with post code */ - outb(POST_OS_BOOT, 0x80); -} diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 437db812af..d914636703 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -969,6 +969,11 @@ static unsigned long southbridge_write_acpi_tables(struct device *device, static void lpc_final(struct device *dev) { + RCBA16(0x3894) = SPI_OPPREFIX; + RCBA16(0x3896) = SPI_OPTYPE; + RCBA32(0x3898) = SPI_OPMENU_LOWER; + RCBA32(0x389c) = SPI_OPMENU_UPPER; + if (acpi_is_wakeup_s3() || IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN)) outb(APM_CNT_FINALIZE, APM_CNT); } diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a02be811f6..a28d703130 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -92,7 +92,6 @@ #ifndef __ACPI__ #if defined(__SMM__) && !defined(__ASSEMBLER__) -void intel_pch_finalize_smm(void); void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); void usb_ehci_disable(pci_devfn_t dev); void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 12e5ea2eb6..a3965d0578 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -25,8 +25,10 @@ #include #include #include +#include #include #include +#include "me.h" #include "pch.h" #include "nvs.h" @@ -284,6 +286,7 @@ static void southbridge_smi_apmc(void) return; } + intel_me_finalize_smm(); intel_pch_finalize_smm(); intel_northbridge_haswell_finalize_smm(); intel_cpu_haswell_finalize_smm(); -- cgit v1.2.3