From 6324759784de0d32e46d8c1af5a2419744a407c9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 10 Feb 2021 13:33:17 +0100 Subject: sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing` The southbridge common SPI support already does this. Tested on Asrock B85M Pro4, internal flashing and MRC cache still work. Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/50479 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/lynxpoint/lpc.c | 9 --------- 1 file changed, 9 deletions(-) (limited to 'src/southbridge/intel/lynxpoint') diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 3685a413f0..9c07c342b9 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -475,13 +475,6 @@ static void pch_set_acpi_mode(void) apm_control(APM_CNT_ACPI_DISABLE); } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - - pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); -} - static void pch_fixups(struct device *dev) { /* Indicate DRAM init done for MRC S3 to know it can resume */ @@ -533,8 +526,6 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); -- cgit v1.2.3