From 45022ae056cdbf58429b77daf2da176306312801 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 1 Oct 2018 19:17:11 +0200 Subject: intel: Use CF9 reset (part 1) Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/southbridge/intel/lynxpoint/Kconfig | 1 - src/southbridge/intel/lynxpoint/Makefile.inc | 5 +---- src/southbridge/intel/lynxpoint/reset.c | 28 ---------------------------- 3 files changed, 1 insertion(+), 33 deletions(-) delete mode 100644 src/southbridge/intel/lynxpoint/reset.c (limited to 'src/southbridge/intel/lynxpoint') diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index dc25b850d8..32485c5c89 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -25,7 +25,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select IOAPIC - select HAVE_HARD_RESET select HAVE_USBDEBUG_OPTIONS select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 7ea0d8bccc..db3454691f 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -36,7 +36,6 @@ endif ramstage-y += rcba.c ramstage-y += me_status.c -ramstage-y += reset.c ramstage-y += watchdog.c ramstage-y += acpi.c @@ -47,7 +46,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c -romstage-y += reset.c early_spi.c rcba.c pmutil.c +romstage-y += early_spi.c rcba.c pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c @@ -55,6 +54,4 @@ ramstage-y += lp_gpio.c smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c endif -postcar-y += reset.c - endif diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c deleted file mode 100644 index 7faadb62df..0000000000 --- a/src/southbridge/intel/lynxpoint/reset.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void do_soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void do_hard_reset(void) -{ - outb(0x06, 0xcf9); -} -- cgit v1.2.3