From 72f4dda6b7d1de5eef1df1d32be4595067c4a15d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 25 Sep 2020 00:23:20 +0200 Subject: sb/intel/lynxpoint/pcie: Fix clock gating routine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The use of `1 < 5` as a bit mask was obviously a typo. Correct it as `1 << 5` to match what Intel doc #493816 (Lynx Point PCH BWG) states. Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45713 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/pcie.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/pcie.c') diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 112c9d3fa3..4a245b1899 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -283,8 +283,7 @@ static void pcie_enable_clock_gating(void) /* Update PECR1 register. */ pci_or_config8(dev, 0xe8, 1); - /* FIXME: Are we supposed to update this register with a constant boolean? */ - pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5)); + pci_or_config8(dev, 0x324, 1 << 5); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) -- cgit v1.2.3