From 3106d0ffce85fe07feefb5c488802aab8e9b42f6 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 12 Aug 2013 13:51:22 -0700 Subject: haswell: Misc updates from 1.6.1 ref code These programming sequences were changed in the latest code. Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/65612 Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/lynxpoint/pcie.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/pcie.c') diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 6a4d75cac2..581b79d1a4 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -649,9 +649,6 @@ static void pch_pcie_early(struct device *dev) pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74); - /* Set undocumented bits in MPC2 register. */ - pcie_update_cfg(dev, 0xd4, ~0, (1 << 12) | (1 << 6)); - /* Set Invalid Recieve Range Check Enable in MPC register. */ pcie_update_cfg(dev, 0xd8, ~0, (1 << 25)); -- cgit v1.2.3