From 249a03b080be30cccecf37354b19fc8b918be447 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 9 Aug 2013 09:06:41 -0700 Subject: lynxpoint: Add devicetree config option to force enable ASPM The PCIe root port has ASPM settings/workarounds that are only applied based on the value of an undocumented bit in PCI config register 0x32C. If that bit is not set for some reason then the settings are not applied. This devicetree config option will force the ASPM settings for each port based on the bit map. Change-Id: I40b08ca9a0ef52742609bac72fb821454a373799 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/65314 Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4453 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/lynxpoint/pcie.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/southbridge/intel/lynxpoint/pcie.c') diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index e133feb9c2..6a4d75cac2 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -495,6 +495,7 @@ static void pch_pcie_early(struct device *dev) int rp; int do_aspm; int is_lp; + struct southbridge_intel_lynxpoint_config *config = dev->chip_info; rp = root_port_number(dev); do_aspm = 0; @@ -542,6 +543,13 @@ static void pch_pcie_early(struct device *dev) } } + /* Allow ASPM to be forced on in devicetree */ + if (config && (config->pcie_port_force_aspm & (1 << (rp - 1)))) + do_aspm = 1; + + printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n", + rp, do_aspm ? "en" : "dis"); + if (do_aspm) { /* Set ASPM bits in MPC2 register. */ pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); -- cgit v1.2.3