From df128a55b183d3d7a6d7ae986f33abffac50f371 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 21 Sep 2019 18:35:37 +0300 Subject: intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/southbridge/intel/lynxpoint/pch.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/pch.h') diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 3f37887567..be4285b1da 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -195,10 +195,6 @@ void mainboard_config_superio(void); #define SMLT 0x1b #define SECSTS 0x1e #define INTR 0x3c -#define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) /* Power Management Control and Status */ #define PCH_PCS 0x84 -- cgit v1.2.3