From 7a1a3ad2ce3403f0379b72d30360e2bed02e9c26 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 24 Jun 2017 21:29:38 -0600 Subject: southbridge/intel: add IS_ENABLED() around Kconfig symbol references MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20350 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/lynxpoint/pch.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/pch.h') diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 655aef1353..c9c9c32acd 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -72,7 +72,7 @@ #define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #define DEFAULT_PMBASE 0x1000 #define DEFAULT_GPIOBASE 0x1400 #define DEFAULT_GPIOSIZE 0x400 @@ -181,7 +181,7 @@ void pch_disable_devfn(device_t dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif void acpi_create_intel_hpet(acpi_hpet_t * hpet); -- cgit v1.2.3