From 7922b468b51eea58c7238f11b21820b8d3747d6b Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 8 Mar 2013 16:34:33 -0800 Subject: lynxpoint: Fix GPIO and PM base reservations The kernel ACPI was not happy with the Add inside a ResourceTemplate (or perhaps within the IO declaration) Instead make a buffer of IO reservations and turn _CRS into a method that updates the buffer depending on the chipset type. This adds an \ISLP() method that checks the chipset LPC device ID to see if it is -LP or -H. It also increases the PM base reservation to 256 bytes and moves both GPIO and PM base to above 0x1000 on -LP chipsets. Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba Signed-off-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/2815 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/southbridge/intel/lynxpoint/pch.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/pch.h') diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index f2953d24c5..ee2efd55bd 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -65,12 +65,13 @@ */ #define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 -#define DEFAULT_PMBASE 0x0500 #if CONFIG_INTEL_LYNXPOINT_LP -#define DEFAULT_GPIOBASE 0x1000 +#define DEFAULT_PMBASE 0x1000 +#define DEFAULT_GPIOBASE 0x1400 #define DEFAULT_GPIOSIZE 0x400 #else +#define DEFAULT_PMBASE 0x500 #define DEFAULT_GPIOBASE 0x480 #define DEFAULT_GPIOSIZE 0x80 #endif -- cgit v1.2.3