From 4bc107bc02529cb1c9288435de2f2e86497f76b3 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 24 Jun 2013 13:14:44 -0700 Subject: lynxpoint: Update LPT-LP PM settings - updates from 1.6.0 ref code - remove the step comments as they are no longer even close - add constants for LPT revisions build and boot on Falco Check that RCBA+2300[1] is set: > mmio_read32 0xfed1e300 0x00000002 Change-Id: I8b3c5fda3f3170455699a7834239cb991603e7a8 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/59821 Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4326 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/southbridge/intel/lynxpoint/pch.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/southbridge/intel/lynxpoint/pch.h') diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 8ef7918df9..70bfee0eba 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -53,6 +53,13 @@ #define PCH_TYPE_LPT_LP 0x9c /* PCH stepping values for LPC device */ +#define LPT_H_STEP_B0 0x02 +#define LPT_H_STEP_C0 0x03 +#define LPT_H_STEP_C1 0x04 +#define LPT_H_STEP_C2 0x05 +#define LPT_LP_STEP_B0 0x02 +#define LPT_LP_STEP_B1 0x03 +#define LPT_LP_STEP_B2 0x04 /* * It does not matter where we put the SMBus I/O base, as long as we -- cgit v1.2.3