From 3f2fe18965fc5404e4d095a25dcb1be48e4040a5 Mon Sep 17 00:00:00 2001 From: Ryan Salsamendi Date: Tue, 4 Jul 2017 13:14:16 -0700 Subject: southbridge/intel/lynxpoint: Fix undefined behavior Fix undefined behavior found by clang's -Wshift-sign-overflow, grep, and source inspection. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68 Signed-off-by: Ryan Salsamendi Reviewed-on: https://review.coreboot.org/20464 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/pch.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/pch.h') diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index d76faf74dd..655aef1353 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -242,7 +242,7 @@ void pch_enable_lpc(void); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 #define PMIR 0xac -#define PMIR_CF9LOCK (1 << 31) +#define PMIR_CF9LOCK (1UL << 31) #define PMIR_CF9GR (1 << 20) /* GEN_PMCON_3 bits */ @@ -389,7 +389,7 @@ void pch_enable_lpc(void); #define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ #define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ #define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ -#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ +#define XHCI_USB3_PORTSC_WPR (1UL << 31) /* Warm Port Reset */ #define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ #define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ #define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ -- cgit v1.2.3