From bf9bc50ec1d1b54a9ae0b86fc1e37e013422186f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 8 Jun 2020 00:12:43 +0200 Subject: sb/intel/lynxpoint: Use PCI bitwise ops Some cases could not be factored out while keeping reproducibility. Also mark some potential bugs with a FIXME comment, since fixing them while also keeping the binary unchanged is pretty much impossible. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I27d6aaa59e12a337f80a6d3387cc9c8ae5949384 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42154 Reviewed-by: Arthur Heymans Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/me_9.x.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/me_9.x.c') diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index d182e317fa..73fbf02ec3 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -541,7 +541,6 @@ void intel_me_finalize_smm(void) { struct me_hfs hfs; u32 reg32; - u16 reg16; mei_base_address = (u32 *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -569,9 +568,8 @@ void intel_me_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); + pci_and_config16(PCH_ME_DEV, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); -- cgit v1.2.3