From 63626b1a4a31588995ff6f0ba42952b6086cbded Mon Sep 17 00:00:00 2001 From: Tristan Corrick Date: Fri, 30 Nov 2018 22:53:50 +1300 Subject: sb/intel/common: Create a common PCH finalise implementation The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak. Lynx Point now benefits from being able to write-protect the flash chip. For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done in bd82x6x. Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is configured, flashrom reports all flash regions as read-only, and does not manage to alter the contents of the flash chip. Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to work as before. Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Signed-off-by: Tristan Corrick Reviewed-on: https://review.coreboot.org/c/29977 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/lpc.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/southbridge/intel/lynxpoint/lpc.c') diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 437db812af..d914636703 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -969,6 +969,11 @@ static unsigned long southbridge_write_acpi_tables(struct device *device, static void lpc_final(struct device *dev) { + RCBA16(0x3894) = SPI_OPPREFIX; + RCBA16(0x3896) = SPI_OPTYPE; + RCBA32(0x3898) = SPI_OPMENU_LOWER; + RCBA32(0x389c) = SPI_OPMENU_UPPER; + if (acpi_is_wakeup_s3() || IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN)) outb(APM_CNT_FINALIZE, APM_CNT); } -- cgit v1.2.3