From 4b519f7c62d55b06c1d99ee6b39a0226475777ad Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 17:36:16 +0100 Subject: sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits For all these southbridges, the lower nibble of PCICMD is read-only. Tested on Asrock B85M Pro4 (Lynxpoint-H), LPC's PCICMD does not change. Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47038 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/lpc.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/lpc.c') diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4286e6ca0a..2872a0b556 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -505,11 +505,6 @@ static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: %s\n", __func__); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ pch_enable_ioapic(dev); -- cgit v1.2.3