From 045f153a4fe2b6e1cb193db01866218d0316f253 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 17 Dec 2012 11:29:10 -0800 Subject: lynxpoint: Add new GPIO interface for Lynxpoint-LP The low power variant of the chipset introduces a completely new interface to the GPIOs. This is a 1KB region and so needs to be moved as well so it does not conflict with other IO regions. Also expose the gpio_get functions to ramstage and move the prototypes to pch.h so they can be used for both GPIO interfaces. Change-Id: I20bc18669525af16de8cdf99f0ccfa9612be63ad Signed-off-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/2648 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'src/southbridge/intel/lynxpoint/acpi') diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index cc59850ec4..03d61ebd3b 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -194,7 +194,22 @@ Device (LPCB) IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI - IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO + +#if CONFIG_INTEL_LYNXPOINT_LP + // LynxPoint LP GPIO is 1KB + IO (Decode16, DEFAULT_GPIOBASE, + DEFAULT_GPIOBASE, 0x1, 0xff) + IO (Decode16, Add(DEFAULT_GPIOBASE, 0x100), + Add(DEFAULT_GPIOBASE, 0x100), 0x1, 0xff) + IO (Decode16, Add(DEFAULT_GPIOBASE, 0x200), + Add(DEFAULT_GPIOBASE, 0x200), 0x1, 0xff) + IO (Decode16, Add(DEFAULT_GPIOBASE, 0x300), + Add(DEFAULT_GPIOBASE, 0x300), 0x1, 0xff) +#else + // LynxPoint GPIO is 128 bytes + IO (Decode16, DEFAULT_GPIOBASE, + DEFAULT_GPIOBASE, 0x1, DEFAULT_GPIOSIZE) +#endif }) } -- cgit v1.2.3