From 8fee9951d30d03b4bca16c198b887c5415418c12 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 29 Jan 2021 23:14:53 +0200 Subject: sb,soc/intel: Add wake source fields in GNVS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For the moment, these are most not used but become a necessity for a unified approach. They would be required for the implementation of _SWS method for OSPM to determine the reason for system waking up. The related hardware registers are present with these platforms. It's expected that ACPI power-management related GNVS entries are grouped together to form a single struct in later works. Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/southbridge/intel/lynxpoint/acpi/globalnvs.asl') diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 979e084161..1b06beb7b6 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -93,6 +93,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xa0), CBMC, 32, // 0xa0 - coreboot mem console pointer + + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } /* Set flag to enable USB charging in S3 */ -- cgit v1.2.3