From 8caa53133f1f0e160f1d6d2aba48a45707cf704a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 21 Jun 2020 18:03:59 +0200 Subject: sb/intel/ibexpeak: Use common early SPI code Change-Id: Ib8cba1ae4fc269c925418965acf6956c1bfe0f79 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42665 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/ibexpeak/bootblock.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) (limited to 'src/southbridge/intel/ibexpeak') diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index b5be3b5143..6ef14a3b08 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -2,23 +2,10 @@ #include #include +#include #include "pch.h" #include "chip.h" -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - u8 reg8; - pci_devfn_t dev = PCH_LPC_DEV; - - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void enable_port80_on_lpc(void) { RCBA32(GCS) &= ~4; @@ -90,7 +77,7 @@ static void early_lpc_init(void) void bootblock_early_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetching_and_caching(); /* Enable RCBA */ pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); -- cgit v1.2.3