From 780e02d1a54598f60f290e7eaba3c0456006ecce Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Tue, 29 Dec 2020 05:12:56 +0200
Subject: ACPI GNVS: Drop APIC, factor out MPEN
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APIC was not referenced anywhere in ASL.

MPEN has references under boards:
getac/p470, roda/rk9, roda/rk886ex.

MPEN has reference also in Intel SpeedStep ASL.

Replace static MPEN with detection of multiple CPUs
installed.

Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/southbridge/intel/ibexpeak/acpi/globalnvs.asl | 4 ++--
 src/southbridge/intel/ibexpeak/include/soc/nvs.h  | 4 ++--
 src/southbridge/intel/ibexpeak/lpc.c              | 8 --------
 3 files changed, 4 insertions(+), 12 deletions(-)

(limited to 'src/southbridge/intel/ibexpeak')

diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
index 314141e65f..174d12f3c7 100644
--- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
+++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
@@ -53,8 +53,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	TMPS,    8,	// 0x25 - Temperature Sensor ID
 	/* Processor Identification */
 	Offset (0x28),
-	APIC,	 8,	// 0x28 - APIC Enabled by coreboot
-	MPEN,	 8,	// 0x29 - Multi Processor Enable
+	,	 8,	// 0x28 -  Enabled by coreboot
+	,	 8,	// 0x29 - Multi Processor Enable
 	PCP0,	 8,	// 0x2a - PDC CPU/CORE 0
 	PCP1,	 8,	// 0x2b - PDC CPU/CORE 1
 	PPCM,	 8,	// 0x2c - Max. PPC state
diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
index 42d588fdc6..5ce88a68b1 100644
--- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h
+++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
@@ -45,8 +45,8 @@ struct __packed global_nvs {
 	u8	tmps; /* 0x25 - Temperature Sensor ID */
 	u8	rsvd3[2];
 	/* Processor Identification */
-	u8	apic; /* 0x28 - APIC enabled */
-	u8	mpen; /* 0x29 - MP capable/enabled */
+	u8	unused_was_apic; /* 0x28 - APIC enabled */
+	u8	unused_was_mpen; /* 0x29 - MP capable/enabled */
 	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
 	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
 	u8	ppcm; /* 0x2c - Max. PPC state */
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index e4d64fd78b..361d3a977b 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -13,7 +13,6 @@
 #include <device/pci_ops.h>
 #include <arch/ioapic.h>
 #include <acpi/acpi.h>
-#include <acpi/acpi_gnvs.h>
 #include <elog.h>
 #include <acpi/acpigen.h>
 #include <string.h>
@@ -23,7 +22,6 @@
 #include <southbridge/intel/common/pciehp.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
 #include <southbridge/intel/common/spi.h>
-#include <soc/nvs.h>
 
 #define NMI_OFF	0
 
@@ -541,12 +539,6 @@ static void pch_lpc_enable(struct device *dev)
 	pch_enable(dev);
 }
 
-void soc_fill_gnvs(struct global_nvs *gnvs)
-{
-	gnvs->apic = 1;
-	gnvs->mpen = 1; /* Enable Multi Processing */
-}
-
 static const char *lpc_acpi_name(const struct device *dev)
 {
 	return "LPCB";
-- 
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