From 685dc56b9f2cf639c8aa72eed948e02044683642 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 4 Jun 2021 12:54:00 +0200 Subject: sb/intel/ibexpeak: Drop P_LVLx support in FADT IO MWAIT redirection is not enabled. The code is missing, but C-states should instead be reported using the _CST ACPI object. Change-Id: I21fd2fa6ee4aa1ed57694549d5cb48159f37af26 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/55217 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/ibexpeak/fadt.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) (limited to 'src/southbridge/intel/ibexpeak') diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index ccd9f57b74..40c8bdc57b 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -11,7 +11,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) struct device *dev = pcidev_on_root(0x1f, 0); struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - int c2_latency; fadt->sci_int = 0x9; @@ -32,12 +31,9 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - c2_latency = chip->c2_latency; - if (!c2_latency) { - c2_latency = 101; /* c2 unsupported */ - } - fadt->p_lvl2_lat = c2_latency; - fadt->p_lvl3_lat = 87; + /* P_LVLx not used */ + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; @@ -54,9 +50,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) if (chip->docking_supported) { fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; } - if (c2_latency < 100) { - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; - } fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; -- cgit v1.2.3