From 12b121cdb450d96309dd96b2ccc25fc5501d2250 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Sun, 18 Aug 2019 16:33:39 +0300
Subject: southbridge/intel: Tidy up preprocessor and headers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34980
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/ibexpeak/lpc.c  |  1 +
 src/southbridge/intel/ibexpeak/me.h   |  5 +----
 src/southbridge/intel/ibexpeak/pch.h  | 19 ++++++++-----------
 src/southbridge/intel/ibexpeak/sata.c |  1 +
 4 files changed, 11 insertions(+), 15 deletions(-)

(limited to 'src/southbridge/intel/ibexpeak')

diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index c7464a05f1..a6bbe64160 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -34,6 +34,7 @@
 #include <cbmem.h>
 #include <string.h>
 #include <cpu/x86/smm.h>
+#include "chip.h"
 #include "pch.h"
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>
diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h
index be65cc5454..5694dd763b 100644
--- a/src/southbridge/intel/ibexpeak/me.h
+++ b/src/southbridge/intel/ibexpeak/me.h
@@ -239,17 +239,14 @@ typedef enum {
 /* Defined in me_status.c for both romstage and ramstage */
 void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
 
-#ifdef __PRE_RAM__
 void intel_early_me_status(void);
 int intel_early_me_init(void);
 int intel_early_me_uma_size(void);
 int intel_early_me_init_done(u8 status);
-#endif
 
-#ifdef __SMM__
 void intel_me_finalize_smm(void);
 void intel_me8_finalize_smm(void);
-#endif
+
 typedef struct {
 	u32       major_version  : 16;
 	u32       minor_version  : 16;
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 24a7905ed2..ee0f9ad555 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -51,29 +51,26 @@
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
 
-#if !defined(__ASSEMBLER__)
-#if !defined(__PRE_RAM__)
-#if !defined(__SIMPLE_DEVICE__)
-#include "chip.h"
-void pch_enable(struct device *dev);
-#endif
 int pch_silicon_revision(void);
 int pch_silicon_type(void);
 int pch_silicon_supported(int type, int rev);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-#if CONFIG(ELOG)
-void pch_log_state(void);
-#endif
-#else /* __PRE_RAM__ */
 void enable_smbus(void);
 void enable_usb_bar(void);
+
+#if ENV_ROMSTAGE
 int smbus_read_byte(unsigned device, unsigned address);
 int smbus_write_byte(unsigned device, unsigned address, u8 data);
 int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
 int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
+#endif
+
 void early_thermal_init(void);
 void southbridge_configure_default_intmap(void);
-#endif
+
+#ifndef __ROMCC__
+#include <device/device.h>
+void pch_enable(struct device *dev);
 #endif
 
 #define MAINBOARD_POWER_OFF	0
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index e03f8b5884..c99e944513 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -25,6 +25,7 @@
 #include <acpi/sata.h>
 #include <types.h>
 
+#include "chip.h"
 #include "pch.h"
 
 typedef struct southbridge_intel_ibexpeak_config config_t;
-- 
cgit v1.2.3